The present invention relates to a power amplifying circuit suitable for activating a speaker, or the like, provided in a headphone and a mobile phone.
The present invention also relates to a DC-DC converter for converting a DC voltage into a DC voltage and, more particularly, to a DC-DC converter for converting a single DC voltage into positive and negative DC voltages.
The present invention also relates to a technique for controlling an output voltage of a power source circuit whose output voltage can be adjusted, like a charge pump.
A power amplifying circuit used for activating a speaker, or the like, provided in a headphone and a mobile phone is required to operate at a low voltage and with low power consumption. For this reason, invalid power consumption other than a power consumption used for activating a load, such as a speaker, must be avoided as much as possible. Under related art technology, a source voltage of a power amplifying circuit is switched according to a level of an input signal or an output signal from the power amplifying circuit in order to minimize useless power consumption. FIG. 21 is a circuit diagram showing an example configuration of a related power amplifying circuit of this type. The power amplifying circuit has a variable power source 820, a predriver 830, and a load drive section 840. In order to prevent complication of a drawing, only a direct connection of the predriver 830 with a load drive section 840 is illustrated in FIG. 21.
The variable power source 820 is supplied with a source voltage from a power source, such as a battery (not shown), and applies a positive source voltage VDD between a high potential power line 821 and a ground line 823, as well as applying a negative source voltage VSS between a low potential power line 822 and the ground line 823. The load drive section 840 has a P channel field effect transistor (hereinafter called simply a “transistor”) 841 and an N channel transistor 842. A source of the P channel transistor 841 is connected to the high potential power line 821, and a source of the N channel transistor 842 is connected to the low potential power line 822. A drain of the P channel transistor 841 and a drain of the N channel transistor 842 are connected together, and a speaker 850, which is a load, is interposed between a ground line and a node between the drains of the P channel transistor 841 and the N channel transistor 842. The predriver 830 is a circuit that activates the load drive section 840 according to an audio signal supplied from an unillustrated previous stage. The predriver 830 has, as circuits for activating the P channel transistor 841, a P channel transistor 831 and a constant current source 832 that are interposed in series between the high potential power line 821 and the low potential power line 822. In addition, the predriver 830 has, as circuits for activating the N channel transistor 842, a constant current source 833 and an N channel transistor 834 that are interposed in series between the high potential power line 821 and the low potential power line 822. The power amplifying circuit performs control for increasing or decreasing the source voltages VDD and VSS output from the variable power source 820 according to an increase or decrease in peak level of a drive waveform of the speaker 850 in such a way that the drive waveform of the speaker 850 that is a load falls within a range between the source voltages VDD and VSS.    [Patent Document 1] JP-A-2008-306269    [Patent Document 2] JP-A-2008-306270
Incidentally, in the related power amplifying circuit, the predriver 830 cannot generate a gate voltage for activating the P channel transistor 841 when the source voltage of the high potential power line 821 and the source voltage of the low potential power line 822 are not sufficiently greater than an absolute value of a threshold voltage of the P channel transistor 841. When the source voltages are not sufficiently greater than a threshold voltage of the N channel transistor 842, the predriver 830 cannot generate a gate voltage for activating the N channel transistor 842. As mentioned above, in order to assure normal operation of the predriver 830, the related power amplifying circuit must hold the source voltage of the high potential power line 821 and the source voltage of the low potential power line 822 at predetermined levels or more and encounters a problem of the inability to sufficiently lessen power consumption.
Various DC-DC converts for generating positive and negative source voltages from a single source voltage are also provided. FIGS. 22A to 22C show respective example DC-DC converters. In the DC-DC converter shown in FIG. 22A, switches SW51 and SW52 are interposed in series between an input power line given a source voltage VDD and a reference power line (a ground line in the example). Further, an inductor L53 and a capacitor C54 are interposed in series between the reference power line and a common node between the switches SW51 and SW52. A common node between the inductor L53 and the capacitor C54 serves as a first voltage output terminal for outputting a source voltage VPP. In the DC-DC converter, a switch SW55 and an inductor L56 are interposed in series between the input power line and the reference power line. A switch SW57 and a capacitor C58 are interposed in series between the reference power line and a common node between the switch SW55 and the inductor L56. A common node between the switch SW57 and the capacitor C58 serves as a second voltage output terminal for outputting a source voltage VMM. The DC-DC converter alternately iterates operation for turning on the switch SW51 and turning off the switch SW52, thereby letting an electric current running toward the capacitor C54 flow into the inductor L53, to thus store electric energy in the inductor L53, and operation for turning off the switch SW51 and turning on the switch SW52, thereby discharging the electric energy stored in the inductor L53, to thus let the electric current running toward the capacitor C54 flow from the inductor L53. As a consequence, the first voltage output terminal outputs the positive source voltage VPP. In parallel with the operation, the DC-DC converter also alternately iterates operation for turning on the switch SW55 and turning off the switch SW57, thereby letting an electric current running toward the reference power line flow into the inductor L56, to thus store electric energy in the inductor L56, and operation for turning off the switch SW55 and turning on the switch SW57, thereby discharging the electric energy stored in the inductor L56, to thus let an electric current running toward the reference power line flow from the capacitor C58 by way of the inductor L56. Consequently, the second voltage output terminal outputs a negative source voltage VMM.
DC-DC converters shown in FIGS. 22B and 22C are so-called charge pumps. In the DC-DC converter shown in FIG. 22B, a switch SW61, a capacitor C62, and a switch SW63 are interposed in series between an input power line given a source voltage VDD and a reference power line (a ground line in the example). Further, a switch SW64 is interposed between the reference power line and a common node between the switch SW61 and the capacitor C62. A switch SW65 and a capacitor C66 are interposed in series between the reference power line and a common node between the switch SW61 and the capacitor C62. The common node between the switch SW65 and the capacitor C66 serves as a first voltage output terminal for outputting the source voltage VPP. Further, a switch SW67 and a capacitor C68 are interposed in series between the reference power line and the common node between the switch SW63 and the capacitor C62. A common node between the switch SW67 and the capacitor C68 serves as a second voltage output terminal for outputting a source voltage VMM. The DC-DC converter alternately performs, for instance, operation for turning on the switches SW61, SW63, and SW65 and turning off the other switches, thereby applying the source voltage VDD to the capacitors C66 and C62 and operation for turning on the switches SW64 and SW67 and turning off the other switches, thereby letting the capacitor C62 apply a voltage −VDD to the capacitor C68. As a consequence, the first voltage output terminal outputs the positive source voltage VPP=VDD, and the second voltage output terminal outputs a negative source voltage VMM=−VDD.
In the DC-DC converter shown in FIG. 22C, switches SW71 and SW72 are interposed in series between an input power line given a source voltage VDD and a reference power line (a ground line in the example). A capacitor C73 and a switch SW74 are interposed in series between the reference power line and a common node between the switches SW71 and SW72. Further, a switch SW75 and a capacitor C76 are interposed in series between the reference power line and a common node between the switches SW71 and SW72. A common node between the switch SW75 and the capacitor C76 acts as a first voltage output terminal for outputting the source voltage VPP. Further, a switch SW77 and a capacitor C78 are interposed in series between the reference power line and a common node between the capacitor C73 and the switch SW74. A common node between the switch SW77 and the capacitor C78 acts as a second voltage output terminal for outputting a source voltage VMM. Moreover, a switch SW79 is interposed between the common node between the switch SW75 and the capacitor C76 and the common node between the capacitor C73 and the switch SW74. The DC-DC converter has two operation modes. In a first operation mode, the DC-DC converter alternately performs operation for turning on the switches SW71, SW74, and SW75 and turning off the other switches, to thus apply the source voltage VDD to the capacitors C73 and C76, and operation for turning on the switches SW72 and SW77 and turning off the other switches, to thus let the capacitor C73 apply a voltage −VDD to the capacitor C78. As a result, the first voltage output terminal outputs the positive source voltage VPP=VDD, and the second voltage output terminal outputs a negative source voltage VMM=−VDD. In a second operation mode, the DC-DC converter alternately performs operation for turning on the switches SW71 and SW79 and turning off the other switches, to thus apply a voltage VDD/2 to each of the capacitors C73 and C76, and operation for turning on the switches SW72 and SW77 and turning off the other switches, thereby letting the capacitor C73 apply a voltage −VDD/2 to the capacitor C78. The first voltage output terminal outputs the positive source voltage VPP=VDD/2, and the second voltage output terminal outputs a negative source voltage VMM=−VDD/2. For instance, JP-A-6-165482 is available as a document pertaining to a charge pump.
Incidentally, the charge pumps shown in FIGS. 22B and 22C among the related DC-DC converters encounter a problem of the ability to output only a source voltage that is equal in level to the source voltage VDD or a source voltage that is an integral sub-multiple of the source voltage VDD. The DC-DC converter shown in FIG. 22A can adjust the positive source voltage VPP by controlling a time during which the switch SW51 is turned on and also can adjust the negative source voltage VMM by controlling a time during which the switch SW55 is turned on. In order to generate the positive source voltage VPP and the negative source voltage VMM, the two inductors L53 and L56 are required. For this reason, when a DC-DC converter including external inductors is configured, there arises a problem of an increase in the number of terminals to which the inductors are to be mounted. Further, when a DC-DC converter including built-in inductors is implemented as a semiconductor integrated circuit, there arises a problem of an increase in chip area.
A charge pump may often be used for an amplifier that activates a speaker included in a stereo headphone, a mobile phone, or the like, (see; for instance, JP-A-2008-306269), as a power source circuit sharing an operating voltage with the amplifier. Since the charge pump can adjust an output voltage, power consumption of an entire system can be reduced, so long as the voltage applied to the amplifier is adjusted according to a level of an output signal and a level of an input signal of the amplifier. An output voltage control circuit (see FIGS. 23A to 23C) including a so-called peak holding circuit is frequently used for adjusting such an output voltage.
FIGS. 23A to 23C are drawings illustrating example configurations of the output voltage control circuits that control an output of a power source circuit 20 (control of an output of the high level voltage VPP to be more precise) that outputs the high level voltage VPP to an amplifier 30L and the low level voltage VMM to an amplifier 30R. In the output voltage control circuit shown in FIG. 23A, a comparator 612 compares an output signal OUTL of the amplifier 30L that activates a left channel speaker 40L with an output signal OUTR of the amplifier 30R that activates a right channel speaker 40R. A switch 614 is switched according to a comparison result. The output voltage control circuit shown in FIG. 23A switches the switch 614 in such a way that either the signal OUTL or the signal OUTR, whichever is larger, is output as a signal N1. In other words, the comparator 612 and the switch 614 make up a peak holding circuit in the configuration shown in FIG. 23A. An operational amplifier 616 shown in FIG. 23A generates a control signal CVPP linked to a level difference (i.e., VPP-N1) between the high level output voltage VPP of the power source circuit 20 and the signal N1 and outputs the thus-generated control signal to the power source circuit 20. Therefore, so long as a configuration is formed so as to let the power source circuit 20 perform processing for adjusting the high level output voltage VPP in such a way that a signal level of the control signal CVPP becomes smaller, the high level output voltage VPP comes to follow either the output signal OUTL of the amplifier 30L or the output signal OUTR of the amplifier 30R, whichever is larger.
The configuration of the output voltage control circuit shown in FIG. 23B includes a resistor 618 and a constant current source 620 added to the output voltage control circuit shown in FIG. 23A. A power circuit to be controlled by the output voltage control circuit, amplifiers sharing an operating voltage with the power circuit, and others, are omitted from FIG. 23B. The resistor 618 and the constant current 620 shown in FIG. 23B make up a peak holding circuit in conjunction with the comparator 612 and the switch 614. As shown in FIG. 23B, the resistor 618 and the constant current source 620 are interposed in series between the switch 614 and a ground, and a voltage appearing in a common node between the resistor 618 and the constant current source 620 is given as the signal N1 to the operational amplifier 616. The signal N1 assumes a value that results from an offset (R×I) linked to a current value I of the constant current source 620 and a resistance value R of the resistor 618 being subtracted from a signal N2 (either the signal OUTL or the signal OUTR, whichever is larger). Therefore; the output voltage control circuit shown in FIG. 23B controls an output of the power circuit according to a level difference (VPP−N1) between the high level output voltage VPP of the power circuit and the signal N1 (N2−R×I).
The configuration of the output voltage control circuit shown in FIG. 23C includes the output voltage control circuit shown in FIG. 23B additionally provided with a comparator 622 and a switch 624. The comparator 622 and the switch 624 shown in FIG. 23C make up a peak holding circuit along with the comparator 612, the switch 614, the resistor 618, and the constant current source 620. The comparator 622 shown in FIG. 23C compares a signal N3 (either the signal OUTL or the signal OUTR, whichever is larger) with a ground potential VSS. The switch 624 is switched according to a comparison result. Specifically, the switch 624 is switched in such a way that either the signal N3 or the ground potential VSS, whichever is larger, is output as the signal N2. Subsequent operation is identical with operation of the output voltage control circuit shown in FIG. 23B.
However, each of the output voltage control circuits respectively shown in FIGS. 23A to 23C includes a comparator and a switch in the peak holding circuit that makes up a principal section of the output voltage control circuit. Since the comparator and the switch account for a comparatively large circuit area, a circuit area of the peak holding circuit including them as constituent elements also becomes large. A problem of difficulty in miniaturization of the output voltage control circuit is encountered.